| Multiplier design based on ancient Indian Vedic Mathematics HD Tiwari, G Gankhuyag, CM Kim, YB Cho 2008 International SoC Design Conference 2, II-65-II-68, 2008 | 264 | 2008 |
| Artificial neural networks for predicting DGPS carrier phase and pseudorange correction A Indriyatmoko, T Kang, YJ Lee, GI Jee, YB Cho, J Kim Gps Solutions 12, 237-247, 2008 | 44 | 2008 |
| Thermal sensor-based multiple object tracking for intelligent livestock breeding W Kim, YB Cho, S Lee IEEE Access 5, 27453-27463, 2017 | 21 | 2017 |
| An indoor positioning system using time-delayed GPS repeater SH Im, GI Jee, YB Cho Proceedings of the 19th International Technical Meeting of the Satellite …, 2006 | 19 | 2006 |
| Comments on" O (n/sup 2/) algorithms for graph planarization Y Takefuji, KC Lee, YB Cho IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1991 | 18 | 1991 |
| Flexible LDPC decoder using stream data processing for 802.11 n and 802.16 e HD Tiwari, HN Bao, YB Cho IEEE Transactions on Consumer Electronics 57 (4), 1505-1512, 2011 | 14 | 2011 |
| CMOS layout design of the hysteresis McCulloch–Pitts neuron T Kurokawa, KC Lee, YB Cho, Y Takefuji Electronics letters 26 (25), 2093-2095, 1990 | 11 | 1990 |
| ERROR CORRECTING SYSTEM BASED ON NEURAL CIRCUITS. Y Takefuji, P Hollis, YP Foo, YB Cho | 10 | 1987 |
| Implementation of DCT based OFDM system HK Gi, DT Honey, MK Chan, BC Yong, Y Kwon 2008 International SoC Design Conference 2, II-41-II-44, 2008 | 9 | 2008 |
| A novel architecture for parallel multi-view HEVC decoder on mobile device W Liu, J Li, YB Cho EURASIP Journal on Image and Video Processing 2017, 1-18, 2017 | 7 | 2017 |
| A parallel IRRWBF LDPC decoder based on stream-based processor HD Tiwari, HN Bao, YB Cho IEEE Transactions on Parallel and Distributed Systems 23 (12), 2198-2204, 2012 | 7 | 2012 |
| An O (1) approximate parallel algorithm for the n-task-n-person assignment problem YB Cho, T Kurokawa, Y Takefuji, HS Kim Proceedings of 1993 International Conference on Neural Networks (IJCNN-93 …, 1993 | 7 | 1993 |
| A neural network parallel algorithm for clique vertex-partition problems N Funabiki, Y Takefuji, KC Lee, YB Cho International journal of electronics 72 (3), 357-372, 1992 | 7 | 1992 |
| Multiplier design based on ancient Vedic mathematics HD Tiwari, G Gankhuyag, CM Kim, YB Cho 978–1-4244-2599-0/08/$25.00© 2008, IEEE, 2008 | 6 | 2008 |
| Hardware architecture for fast motion estimation in H. 264/AVC video coding MS Byeon, YM Shin, YB Cho IEICE transactions on fundamentals of electronics, communications and …, 2006 | 6 | 2006 |
| A parallel neural network computing for the maximum clique problem KC Lee, N Funabiki, YB Cho, Y Takefuji International Joint Conference on Neural Networks, Singapore, 905-910, 1991 | 6 | 1991 |
| Study on the Implementation of a Simple and Effective Memory System for an AI Chip T Kim, S Park, Y Cho Electronics 10 (12), 1399, 2021 | 5 | 2021 |
| High-throughput HW-SW implementation for MV-HEVC decoder W Liu, W Li, PS Un, YB Cho 2018 International SoC Design Conference (ISOCC), 226-228, 2018 | 4 | 2018 |
| GPU_CPU based parallel architecture for reduction in power consumption XJ Zhao, MZ Yu, YB Cho 2012 IEEE Global High Tech Congress on Electronics, 182-185, 2012 | 3 | 2012 |
| Low Power IMDCT Design on FPGA NX Giap, HD Tiwari, YB Cho, CM Kim 대한전자공학회 학술대회, 530-532, 2009 | 3 | 2009 |
