Следене
Jeremy Levitt
Jeremy Levitt
Потвърден имейл адрес: mentor.com
Заглавие
Позовавания
Позовавания
Година
Validity checking for combinations of theories with equality
C Barrett, DL Dill, J Levitt
FMCAD 96, 187-201, 1996
2681996
A decision procedure for an extensional theory of arrays
A Stump, CW Barrett, DL Dill, J Levitt
Proceedings 16th Annual IEEE Symposium on Logic in Computer Science, 29-37, 2001
2122001
A decision procedure for bit-vector arithmetic
CW Barrett, DL Dill, JR Levitt
Proceedings of the 35th Annual Design Automation Conference, 522-527, 1998
1801998
A software-hardware cosynthesis approach to digital system simulation
KA Olukotun, R Helaihel, J Levitt, R Ramirez
IEEE Micro 14 (4), 48-58, 1994
791994
A general method for compiling event-driven simulations
RS French, MS Lam, JR Levitt, K Olukotun
Proceedings of the 32nd Annual ACM/IEEE Design Automation Conference, 151-156, 1995
771995
Measure of analysis performed in property checking
JR Levitt, C Gauthron, CMR Ho, PF Yeung, KC Mulam, R Sathianathan
US Patent 6,848,088, 2005
54*2005
A scalable formal verification methodology for pipelined microprocessors
J Levitt, K Olukotun
Proceedings of the 33rd annual Design Automation Conference, 558-563, 1996
461996
Functional test selection based on unsupervised support vector analysis
O Guzey, LC Wang, J Levitt, H Foster
Proceedings of the 45th annual Design Automation Conference, 262-267, 2008
452008
Verifying correct pipeline implementation for microprocessors
J Levitt, K Olukotun
iccad, 162-169, 1997
451997
Measure of analysis performed in property checking
JR Levitt, C Gauthron, CMR Ho, PF Yeung, KC Mulam, R Sathianathan
US Patent 6,848,088, 2005
442005
Measure of analysis performed in property checking
JR Levitt, C Gauthron, CMR Ho, PF Yeung, KC Mulam, R Sathianathan
US Patent 6,848,088, 2005
442005
Selection of initial states for formal verification
JAG Seawright, R Sathianathan, CG Gauthron, JR Levitt, KC Mulam, ...
US Patent 7,454,324, 2008
432008
Formal verification techniques for digital systems
JR Levitt
stanford university, 1999
321999
Reuse of learned information to simplify functional verification of a digital circuit
J Levitt, C Gauthron, C Barrett, L Widdoes
US Patent App. 10/340,555, 2007
212007
Increasing the efficiency of simulation-based functional verification through unsupervised support vector analysis
O Guzey, LC Wang, JR Levitt, H Foster
IEEE transactions on computer-aided design of integrated circuits and …, 2009
182009
Automatic assume guarantee analysis for assertion-based formal verification
D Wang, J Levitt
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
162005
Measure of analysis performed in property checking
JR Levitt, C Gauthron, CR Ho, PF Yeung, KC Mulam, R Sathianathan
US Patent 7,318,205, 2008
132008
Using formal techniques to verify system on chip reset schemes
K Liu, P Yang, J Levitt, M Berman, M Eslinger
Proc. DVCon, 2013
102013
Clock model for formal verification of a digital circuit description
JAG Seawright, JR Levitt, C Gauthron
US Patent 7,487,483, 2009
92009
Clock model for formal verification of a digital circuit description
JAG Seawright, JR Levitt, C Gauthron
US Patent 7,487,483, 2009
82009
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