Modeling of charge and quantum capacitance in low effective mass III-V FinFETs MD Ganeriwala, C Yadav, NR Mohapatra, S Khandelwal, C Hu, ...
IEEE Journal of the Electron Devices Society 4 (6), 396-401, 2016
14 2016 Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors MD Ganeriwala, C Yadav, FG Ruiz, EG Marin, YS Chauhan, ...
IEEE Transactions on Electron Devices 64 (12), 4889-4896, 2017
13 2017 Compact Modeling of Gate Capacitance in III–V Channel Quadruple-Gate FETs C Yadav, MD Ganeriwala, NR Mohapatra, A Agarwal, YS Chauhan
IEEE Transactions on Nanotechnology 16 (4), 703-710, 2017
10 2017 A compact charge and surface potential model for III–V cylindrical nanowire transistors MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
IEEE Transactions on Electron Devices 66 (1), 73-79, 2018
8 2018 Anomalous Width Dependence of Gate Current in High- P Duhan, MD Ganeriwala, VR Rao, NR Mohapatra
IEEE Electron Device Letters 36 (8), 739-741, 2015
6 2015 A Bottom-Up Scalable Compact Model for Quantum Confined Nanosheet FETs MD Ganeriwala, A Singh, A Dubey, R Kaur, NR Mohapatra
IEEE Transactions on Electron Devices, 2021
3 2021 A compact model for III–V nanowire electrostatics including band non-parabolicity MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
Journal of Computational Electronics, 2019
3 2019 An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors A Gupta, M Ganeriwala, NR Mohapatra
2019 32nd International Conference on VLSI Design and 2019 18th …, 2019
3 2019 Computationally efficient analytic charge model for III-V cylindrical nanowire transistors MD Ganeriwala, EG Marin, FG Ruiz, NR Mohapatra
2018 Joint International EUROSOI Workshop and International Conference on …, 2018
2 2018 Reconfigurable frequency multipliers based on graphene field-effect transistors A Toral-Lopez, EG Marin, F Pasadas, MD Ganeriwala, FG Ruiz, ...
Discover Nano 18 (1), 1-10, 2023
1 2023 Non-Volatile Resistive Switching of Polymer Residues in 2D Material Memristors D Braun, MD Ganeriwala, L Völkel, K Ran, S Lukas, EG Marín, O Hartwig, ...
arXiv preprint arXiv:2309.13900, 2023
1 2023 A simplified approach to include confinement induced band structure changes into the NsFET compact model A Singh, MD Ganeriwala, R Kaur, NR Mohapatra
2022 IEEE International Conference on Emerging Electronics (ICEE), 1-5, 2022
1 2022 Insights into the Mechanical and Electrical Properties of a Metal–Phosphorene Interface: An Ab Initio Study with a Wide Range of Metals A Ghaffar, MD Ganeriwala, K Hongo, R Maezono, NR Mohapatra
ACS omega 6 (11), 7795-7803, 2021
1 2021 Effect of Pregate Carbon Implant on Narrow Width Behavior and Performance of High- NR Mohapatra, MD Ganeriwala
IEEE Transactions on Electron Devices 63 (7), 2708-2713, 2016
1 2016 A unified compact model for electrostatics of III–V GAA transistors with different geometries MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
Journal of Computational Electronics 20 (5), 1676-1684, 2021
2021 Significance of L-valley charges and a method to include it in electrostatic model of III-V GAA FETs MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020
2020 Compact electrostatics and transport model for high mobility iii-v channel gate-all-around MOS transistors MD Ganeriwala
Indian Institute of Technology Gandhinagar, 2020
2020 Capacitance and Surface Potential Model for III-V Double-Gate FET SGM Chandran, MD Ganeriwala, NR Mohapatra
2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS), 1-5, 2019
2019 Charge and Capacitance Compact Model for III-V Quadruple-Gate FETs With Square Geometry MD Ganeriwala, EG Marin, FG Ruiz, NR Mohapatra
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK …, 2019
2019 A Simple Charge and Capacitance Compact Model for Asymmetric III-V DGFETs using CCDA MD Ganeriwala, SGM GM, NR Mohapatra
4th IEEE International Conference on Emerging Electronics, Bangalore, 2018, 2018
2018 
Enrique G. MarinDepartamento Electrónica y Tecnología de Computadores. Universidad de GranadaПотвърден имейл адрес: ugr.es
