Следене
Thomas Parnell
Thomas Parnell
IBM Research
Потвърден имейл адрес: zurich.ibm.com - Начална страница
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Позовавания
Позовавания
Година
Neuromorphic computing with multi-memristive synapses
I Boybat, M Le Gallo, SR Nandakumar, T Moraitis, T Parnell, T Tuma, ...
Nature communications 9 (1), 2514, 2018
5382018
Temporal correlation detection using computational phase-change memory
A Sebastian, T Tuma, N Papandreou, M Le Gallo, L Kull, T Parnell, ...
Nature Communications 8 (1), 1115, 2017
2012017
Modelling of the threshold voltage distributions of sub-20nm NAND flash memory
T Parnell, N Papandreou, T Mittelholzer, H Pozidis
2014 IEEE Global Communications Conference, 2351-2356, 2014
872014
Data encoding in solid-state storage devices
T Mittelholzer, N Papandreou, T Parnell, C Pozidis
US Patent 9,734,012, 2017
762017
Scalable and interpretable product recommendations via overlapping co-clustering
R Heckel, M Vlachos, T Parnell, C Dünner
2017 IEEE 33rd International Conference on Data Engineering (ICDE), 1033-1044, 2017
692017
Scalable and interpretable product recommendations via overlapping co-clustering
R Heckel, M Vlachos, T Parnell, C Dünner
2017 IEEE 33rd International Conference on Data Engineering (ICDE), 1033-1044, 2017
692017
Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems
N Papandreou, T Parnell, H Pozidis, T Mittelholzer, E Eleftheriou, C Camp, ...
Proceedings of the 24th edition of the great lakes symposium on VLSI, 151-156, 2014
362014
Extending useful life of a non-volatile memory by health grading
CJ Camp, I Koltsidas, N Papandreou, T Parnell, RA Pletka, C Pozidis, ...
US Patent 9,558,107, 2017
352017
Benchmarking and optimization of gradient boosting decision tree algorithms
A Anghel, N Papandreou, T Parnell, A De Palma, H Pozidis
arXiv preprint arXiv:1809.04559, 2018
322018
Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,251,909, 2016
302016
Characterization and analysis of bit errors in 3D TLC NAND flash memory
N Papandreou, H Pozidis, T Parnell, N Ioannou, R Pletka, S Tomic, ...
2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019
272019
Device for selecting a level for at least one read voltage
CJ Camp, ES Eleftheriou, T Mittelholzer, T Parnell, N Papandreou, ...
US Patent 9,639,462, 2017
272017
Page-level health equalization
CJ Camp, T Mittelholzer, N Papandreou, T Parnell, C Pozidis
US Patent 9,990,279, 2018
252018
Updating prefix codes for pseudo-dynamic data compression
CJ Camp, C Pozidis, N Papandreou, RA Pletka, T Mittelholzer, T Parnell, ...
US Patent 10,700,702, 2020
242020
From random block corruption to privilege escalation: A filesystem attack vector for rowhammer-like attacks.
A Kurmus, N Ioannou, N Papandreou, TP Parnell
WOOT, 2017
242017
Snap ML: A hierarchical framework for machine learning
C Dünner, T Parnell, D Sarigiannis, N Ioannou, A Anghel, G Ravi, ...
Advances in Neural Information Processing Systems 31, 2018
232018
Addressing interpretability and cold-start in matrix factorization for recommender systems
M Vlachos, C Dünner, R Heckel, VG Vassiliadis, T Parnell, K Atasu
IEEE Transactions on Knowledge and Data Engineering 31 (7), 1253-1266, 2018
222018
NAND Flash Basics & Error Characteristics: Why Do We Need Smart Controllers
T Parnell, R Pletka
Flash Memory Summit 3 (4.2), 3.4, 2016
222016
Techniques for dynamically adjusting over-provisioning space of a flash controller based on workload characteristics
CJ Camp, TJ Fisher, AD Fry, N Ioannou, T Parnell, RA Pletka, S Tomic
US Patent 10,592,110, 2020
192020
State-dependent read voltage threshold adaptation for nonvolatile memory
TJ Fisher, T Mittelholzer, N Papandreou, T Parnell, C Pozidis
US Patent 10,236,067, 2019
192019
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