ISPD 2018 initial detailed routing contest and benchmarks S Mantik, G Posser, WK Chow, Y Ding, WH Liu
Proceedings of the 2018 International Symposium on Physical Design, 140-143, 2018
65 2018 Effective Method for Simultaneous Gate Sizing and G Flach, T Reimann, G Posser, M Johann, R Reis
IEEE transactions on computer-aided design of integrated circuits and …, 2014
60 2014 ISPD 2019 initial detailed routing contest and benchmark with advanced routing rules WH Liu, S Mantik, WK Chow, Y Ding, A Farshidi, G Posser
Proceedings of the 2019 International Symposium on Physical Design, 147-151, 2019
39 2019 A systematic approach for analyzing and optimizing cell-internal signal electromigration G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 486-491, 2014
24 2014 Simultaneous gate sizing and vt assignment using fanin/fanout ratio and simulated annealing T Reimann, G Posser, G Flach, M Johann, R Reis
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2549-2552, 2013
24 2013 FinFET cells with different transistor sizing techniques against PVT variations AL Zimpeck, C Meinhardt, G Posser, R Reis
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 45-48, 2016
22 2016 Cell-internal electromigration: Analysis and pin placement based optimization G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
20 2015 Analyzing the electromigration effects on different metal layers and different wire lengths G Posser, V Mishra, R Reis, SS Sapatnekar
2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014
19 2014 Gate sizing minimizing delay and area G Posser, G Flach, G Wilke, R Reis
2011 IEEE Computer Society Annual Symposium on VLSI, 315-316, 2011
15 2011 Cell-level signal electromigration SS Sapatnekar, V Mishra, P Jain, G Posser, R Reis
US Patent 9,665,680, 2017
14 2017 Electromigration aware circuits by using special signal non-default routing rules L de Paris, G Posser, R Reis
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2795-2798, 2016
10 2016 Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities G Flach, T Reimann, G Posser, M Johann, R Reis
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 84-89, 2013
10 2013 Gate sizing using geometric programming G Posser, G Flach, G Wilke, R Reis
Analog Integrated Circuits and Signal Processing 73, 831-840, 2012
10 2012 Variabilidade em FinFETs C Meinhardt
9 2014 Reducing the number of transistors with gate clustering C Conceição, G Posser, R Reis
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 163-166, 2016
7 2016 Process variability in FinFET standard cells with different transistor sizing techniques AL Zimpeck, C Meinhardt, G Posser, R Reis
2015 IEEE International Conference on Electronics, Circuits, and Systems …, 2015
7 2015 Perfomance improvement with dedicated transistor sizing for mosfet and finfet devices G Posser, J Belomo, C Meinhardt, R Reis
2014 IEEE Computer Society Annual Symposium on VLSI, 418-423, 2014
7 2014 A study on layout quality of automatic generated cells G Posser, A Ziesemer, D Guimares, G Wilke, R Reis
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
7 2010 Electromigration Inside Logic Cells G Posser, SS Sapatnekar, R Reis
Springer, 2017
6 2017 Reducing the signal electromigration effects on different logic gates by cell layout optimization G Posser, L De Paris, V Mishra, P Jain, R Reis, SS Sapatnekar
2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2015
6 2015 
Ricardo Augusto da Luz ReisUFRGSПотвърден имейл адрес: inf.ufrgs.br
