| Chip and wafer integration process using vertical connections HB Pogge, R Yu, C Prasad, C Narayan US Patent 6,599,778, 2003 | 421 | 2003 |
| High density chip carrier with integrated passive devices MP Chudzik, RH Dennard, R Divakaruni, BK Furman, R Jammy, ... US Patent 7,030,481, 2006 | 410 | 2006 |
| Fuse processing using dielectric planarization pillars L Clevenger, LLC Hsu, C Narayan, JK Stephens, M Wise US Patent 6,420,216, 2002 | 222 | 2002 |
| Copper recess process with application to selective capping and electroless plating ST Chen, TJ Dalton, KM Davis, CK Hu, FF Jamin, SK Kaldor, M Krishnan, ... US Patent 6,975,032, 2005 | 154 | 2005 |
| System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient C Kothandaraman, SSK Iyer, S Iyer, C Narayan US Patent 6,624,499, 2003 | 108 | 2003 |
| Reliability and design qualification of a sub-micron tungsten silicide E-Fuse WR Tonti, JA Fifield, J Higgins, WH Guthrie, W Berry, C Narayan 2004 IEEE International Reliability Physics Symposium. Proceedings, 152-156, 2004 | 90 | 2004 |
| Device to monitor and control the temperature of electronic chips to enhance reliability DA Lewis, C Narayan US Patent 5,569,950, 1996 | 89 | 1996 |
| Electronic structures having a joining geometry providing reduced capacitive loading A Deutsch, DA Lewis, C Narayan, AL Plachy US Patent 5,471,090, 1995 | 81 | 1995 |
| Product specific sub-micron e-fuse reliability and design qualification WR Tont, JA Fifield, J Higgins, WH Guthrie, W Berry, C Narayan IEEE International Integrated Reliability Workshop Final Report, 2003, 36-40, 2003 | 79 | 2003 |
| Multi-layer thin film structure and parallel processing method for fabricating same G Arjavalingam, A Deutsch, FE Doany, BK Furman, DJ Hunt, C Narayan, ... US Patent 5,258,236, 1993 | 67 | 1993 |
| Scaling tape-recording areal densities to 100 Gb/in2 AJ Argumedo, D Berman, RG Biskeborn, G Cherubini, RD Cideciyan, ... IBM journal of research and development 52 (4.5), 513-527, 2008 | 57 | 2008 |
| Flat panel display containing black matrix polymer M Angelopoulos, A Afzali-Ardakani, C Feger, C Narayan US Patent 5,619,357, 1997 | 55 | 1997 |
| Method for fabricating multi-layer thin film structure having a separation layer G Arjavalingam, A Deutsch, FE Doany, BK Furman, DJ Hunt, C Narayan, ... US Patent 5,534,094, 1996 | 52 | 1996 |
| Laser release process to obtain freestanding multilayer metal-polyimide circuits FE Doany, C Narayan IBM Journal of Research and Development 41 (1.2), 151-157, 1997 | 49 | 1997 |
| Conductor-insulator-conductor structure JP Gambino, C Narayan, T Kirihata US Patent 6,081,021, 2000 | 47 | 2000 |
| Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells T Kirihata, D Storaska, C Narayan, W Tonti, C Bertin, N Van Heel US Patent 6,266,272, 2001 | 43 | 2001 |
| Variable resistor structure and method for forming and programming a variable resistor for electronic circuits LLC Hsu, C Narayan, CJ Radens US Patent 6,700,161, 2004 | 42 | 2004 |
| Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal G DiGiacomo, JI Kim, C Narayan, S Purushothaman US Patent 5,367,195, 1994 | 42 | 1994 |
| Electrical fuses with tight pitches and method of fabrication in semiconductors C Narayan, A Brintzinger, G Daniel, F Einspruch US Patent 6,008,523, 1999 | 41 | 1999 |
| Defect management engine for semiconductor memories and memory systems T Kirihata, LLC Hsu, C Narayan US Patent 6,141,267, 2000 | 40 | 2000 |
