Jongeun Lee
Jongeun Lee
Professor in EE, UNIST
Потвърден имейл адрес: unist.ac.kr - Начална страница
Заглавие
Позовавания
Позовавания
Година
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks
K Kim, J Kim, J Yu, J Seo, J Lee, K Choi
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
1632016
Compilation approach for coarse-grained reconfigurable architectures
J Lee, K Choi, ND Dutt
IEEE Design & Test of Computers 20 (1), 26-33, 2003
1132003
Efficient FPGA acceleration of convolutional neural networks using logical-3D compute array
A Rahman, J Lee, K Choi
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
972016
A new stochastic computing multiplier with application to deep convolutional neural networks
H Sim, J Lee
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
912017
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
J Lee, K Choi, N Dutt
IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002 …, 2002
822002
An algorithm for mapping loops onto coarse-grained reconfigurable architectures
J Lee, K Choi, ND Dutt
ACM Sigplan Notices 38 (7), 183-188, 2003
712003
Reconfigurable ALU array architecture with conditional execution
J Lee, Y Kim, J Jung, S Kang, K Choi
International Soc. Design Conference (ISOOC)[online] Oct 25, 2004
652004
An energy-efficient random number generator for stochastic circuits
K Kim, J Lee, K Choi
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 256-261, 2016
522016
SDRM: Simultaneous determination of regions and function-to-region mapping for scratchpad memories
A Pabalkar, A Shrivastava, A Kannan, J Lee
International Conference on High-Performance Computing, 569-582, 2008
492008
A software solution for dynamic stack management on scratch pad memory
A Kannan, A Shrivastava, A Pabalkar, J Lee
2009 Asia and South Pacific Design Automation Conference, 612-617, 2009
482009
Improving performance of nested loops on reconfigurable array processors
Y Kim, J Lee, TX Mai, Y Paek
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-23, 2012
402012
A compiler optimization to reduce soft errors in register files
J Lee, A Shrivastava
ACM Sigplan Notices 44 (7), 41-49, 2009
402009
Static analysis to mitigate soft errors in register files
J Lee, A Shrivastava
2009 Design, Automation & Test in Europe Conference & Exhibition, 1367-1372, 2009
362009
High throughput data mapping for coarse-grained reconfigurable architectures
Y Kim, J Lee, A Shrivastava, JW Yoon, D Cho, Y Paek
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
352011
Approximate de-randomizer for stochastic circuits
K Kim, J Lee, K Choi
2015 International SoC Design Conference (ISOCC), 123-124, 2015
332015
Accurate and efficient stochastic computing hardware for convolutional neural networks
J Yu, K Kim, J Lee, K Choi
2017 IEEE International Conference on Computer Design (ICCD), 105-112, 2017
322017
Operation and data mapping for cgras with multi-bank memory
Y Kim, J Lee, A Shrivastava, Y Paek
ACM Sigplan Notices 45 (4), 17-26, 2010
312010
Scalable stochastic-computing accelerator for convolutional neural networks
H Sim, D Nguyen, J Lee, K Choi
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 696-701, 2017
302017
Static analysis of register file vulnerability
J Lee, A Shrivastava
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
292011
A compiler-microarchitecture hybrid approach to soft error reduction for register files
J Lee, A Shrivastava
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
292010
Системата не може да изпълни операцията сега. Опитайте отново по-късно.
Статии 1–20