Krishna Saraswat
Krishna Saraswat
Professor of Electrical Engineering, Stanford University
Потвърден имейл адрес: stanford.edu - Начална страница
3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
K Banerjee, SJ Souri, P Kapur, KC Saraswat
Proceedings of the IEEE 89 (5), 602-633, 2001
Interconnect limits on gigascale integration (GSI) in the 21st century
JA Davis, R Venkatesan, A Kaloyeros, M Beylansky, SJ Souri, K Banerjee, ...
Proceedings of the IEEE 89 (3), 305-324, 2001
Nanometre-scale germanium photodetector enhanced by a near-infrared dipole antenna
L Tang, SE Kocabas, S Latif, AK Okyay, DS Ly-Gagnon, KC Saraswat, ...
Nature Photonics 2 (4), 226-229, 2008
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip
MM Shulaker, G Hills, RS Park, RT Howe, K Saraswat, HSP Wong, S Mitra
Nature 547 (7661), 74-78, 2017
Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and≪ 60mV/dec subthreshold slope
T Krishnamohan, D Kim, S Raghunathan, K Saraswat
2008 IEEE International Electron Devices Meeting, 1-3, 2008
Germanium nanowire field-effect transistors with and high-κ gate dielectrics
D Wang, Q Wang, A Javey, R Tu, H Dai, H Kim, PC McIntyre, ...
Applied Physics Letters 83 (12), 2432-2434, 2003
Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition
CD English, G Shine, VE Dorgan, KC Saraswat, E Pop
Nano letters 16 (6), 3824-3830, 2016
Effect of scaling of interconnections on the time delay of VLSI circuits
KC Saraswat, F Mohammadi
IEEE Transactions on Electron Devices 29 (4), 645-650, 1982
Achieving direct band gap in germanium through integration of Sn alloying and external strain
S Gupta, B Magyari-Köpe, Y Nishi, KC Saraswat
Journal of Applied Physics 113 (7), 2013
Dopant segregation in polycrystalline silicon
MM Mandurah, KC Saraswat, CR Helms, TI Kamins
Journal of applied physics 51 (11), 5755-5763, 1980
On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates
K Martens, CO Chui, G Brammertz, B De Jaeger, D Kuzum, M Meuris, ...
IEEE Transactions on Electron Devices 55 (2), 547-556, 2008
Two-dimensional thermal oxidation of silicon. II. Modeling stress effects in wet oxides
DB Kao, JP Mcvittie, WD Nix, KC Saraswat
IEEE transactions on electron devices 35 (1), 25-37, 1988
Germanium MOS capacitors incorporating ultrathin high-/spl kappa/gate dielectric
CO Chui, S Ramanathan, BB Triplett, PC McIntyre, KC Saraswat
IEEE Electron Device Letters 23 (8), 473-475, 2002
Activation and diffusion studies of ion-implanted and dopants in germanium
CO Chui, K Gopalakrishnan, PB Griffin, JD Plummer, KC Saraswat
Applied physics letters 83 (16), 3275-3277, 2003
Multiple Si layer ICs: Motivation, performance analysis, and design implications
SJ Souri, K Banerjee, A Mehrotra, KC Saraswat
Proceedings of the 37th Annual Design Automation Conference, 213-220, 2000
Thermal/microwave remote plasma multiprocessing reactor and method of use
MM Moslehi, KC Saraswat
US Patent 4,913,929, 1990
Electrical and materials properties of gate dielectrics grown by atomic layer chemical vapor deposition
CM Perkins, BB Triplett, PC McIntyre, KC Saraswat, S Haukka, ...
Applied Physics Letters 78 (16), 2357-2359, 2001
Two-dimensional thermal oxidation of silicon—I. Experiments
DB Kao, JP McVittie, WD Nix, KC Saraswat
IEEE Transactions on Electron Devices 34 (5), 1008-1017, 1987
The effect of fluorine in silicon dioxide gate dielectrics
PJ Wright, KC Saraswat
IEEE Transactions on Electron Devices 36 (5), 879-889, 1989
Technology and reliability constrained future copper interconnects. I. Resistance modeling
P Kapur, JP McVittie, KC Saraswat
IEEE Transactions on electron devices 49 (4), 590-597, 2002
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