Ajey Jacob
Ajey Jacob
Information Sciences Institute, University of Southern California
Потвърден имейл адрес: isi.edu
14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications
Z Krivokapic, U Rana, R Galatage, A Razavieh, A Aziz, J Liu, J Shi, ...
2017 IEEE International Electron Devices Meeting (IEDM), 15.1. 1-15.1. 4, 2017
Electric-field-controlled ferromagnetism in high-Curie-temperature Mn0.05Ge0.95 quantum dots
F Xiu, Y Wang, J Kim, A Hong, J Tang, AP Jacob, J Zou, KL Wang
Nature Materials 9 (4), 337-344, 2010
45nm CMOS-silicon photonics monolithic technology (45CLO) for next-generation, low power and high speed optical interconnects
M Rakowski, C Meagher, K Nummy, A Aboketaf, J Ayala, Y Bian, B Harris, ...
Optical Fiber Communication Conference, T3H. 3, 2020
Scaling challenges for advanced CMOS devices
AP Jacob, R Xie, MG Sung, L Liebmann, RTP Lee, B Taylor
International Journal of High Speed Electronics and Systems 26 (01n02), 1740001, 2017
Performance of magnetic quantum cellular automata and limitations due to thermal noise
FM Spedalieri, AP Jacob, DE Nikonov, VP Roychowdhury
IEEE Transactions on Nanotechnology 10 (3), 537-546, 2010
Single Crystalline Ge1-xMnx Nanowires as Building Blocks for Nanoelectronics
MI Van Der Meulen, N Petkov, MA Morris, O Kazakova, X Han, KL Wang, ...
Nano Letters 9 (1), 50-56, 2009
10 Gbit/s data modulation using 1.3 µm InGaAs quantum dot lasers
M Kuntz, G Fiol, M Lämmlin, C Schubert, AR Kovsh, A Jacob, A Umbach, ...
Electronics letters 41 (5), 1, 2005
Methods of forming FinFET devices with alternative channel materials
WP Maszara, AP Jacob, NV LiCausi, JA Fronheiser, K Akarvardar
US Patent 8,673,718, 2014
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
R Xie, WJ Taylor Jr, AP Jacob
US Patent 9,318,552, 2016
Towards low-loss monolithic silicon and nitride photonic building blocks in state-of-the-art 300mm CMOS foundry
Y Bian, J Ayala, C Meagher, B Peng, M Rakowski, A Jacob, K Nummy, ...
Frontiers in Optics, FW5D. 2, 2020
Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
J Fronheiser, AP Jacob, WP Maszara, K Akarvardar
US Patent App. 13/839,998, 2014
Integrated display system with multi-color light emitting diodes (LEDs)
S Banna, S Jha, D Nayak, AP Jacob
US Patent 10,037,981, 2018
Electrical isolation of FinFET active region by selective oxidation of sacrificial layer
MK Akarvardar, JA Fronheiser, AP Jacob
US Patent 9,716,174, 2017
Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
X Cai, R Xie, K Cheng, A Khakifirooz, AP Jacob, WP Maszara
US Patent 9,412,822, 2016
Fin transformation process and isolation structures facilitating different Fin isolation schemes
AP Jacob, K Cheng, BB Doris, N Loubet, P Khare, R Divakaruni
US Patent 9,349,730, 2016
Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process
R Xie, A Knorr, AP Jacob, M Hargrove
US Patent 9,147,730, 2015
Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process
BJ Pawlak, S Bentley, A Jacob
US Patent 8,716,156, 2014
Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
MK Akarvardar, AP Jacob
US Patent 9,385,233, 2016
Methods of forming substrates comprised of different semiconductor materials and the resulting device
BJ Pawlak, S Bentley, A Jacob
US Patent 9,368,578, 2016
Системата не може да изпълни операцията сега. Опитайте отново по-късно.
Статии 1–20