Smail NIAR
Smail NIAR
Université Polytechnique Hauts-de-France, France
Verified email at - Homepage
Cited by
Cited by
An effective and distributed particle swarm optimization algorithm for flexible job-shop scheduling problem
M Nouiri, A Bekrar, A Jemai, S Niar, AC Ammari
Journal of Intelligent Manufacturing 29 (3), 603-615, 2018
Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators
G Zhong, A Prakash, Y Liang, T Mitra, S Niar
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
Two stage particle swarm optimization to solve the flexible job shop predictive scheduling problem considering possible machine breakdowns
M Nouiri, A Bekrar, A Jemai, D Trentesaux, AC Ammari, S Niar
Computers & Industrial Engineering 112, 595-606, 2017
Gaspard2: from MARTE to SystemC simulation
É Piel, RB Atitallah, P Marquet, S Meftali, S Niar, A Etien, JL Dekeyser, ...
proc. of the DATE 8, 2008
System-level power estimation tool for embedded processor based platforms
SK Rethinagiri, O Palomar, R Ben Atitallah, S Niar, O Unsal, ...
Proceedings of the 6th Workshop on Rapid Simulation and Performance …, 2014
Estimating energy consumption for an MPSoC architectural exploration
RB Atitallah, S Niar, A Greiner, S Meftali, JL Dekeyser
International Conference on Architecture of Computing Systems, 298-310, 2006
An MPSoC performance estimation framework using transaction level modeling
RB Atitallah, S Niar, S Meftali, JL Dekeyser
13th IEEE International Conference on Embedded and Real-Time Computing …, 2007
A parallel tabu search algorithm for the 0-1 multidimensional knapsack problem
S Niar, A Freville
Proceedings 11th International Parallel Processing Symposium, 512-516, 1997
Design space exploration of multiple loops on FPGAs using high level synthesis
G Zhong, V Venkataramani, Y Liang, T Mitra, S Niar
2014 IEEE 32nd international conference on computer design (ICCD), 456-463, 2014
MPSoC power estimation framework at transaction level modeling
RB Atitallah, S Niar, JL Dekeyser
2007 Internatonal Conference on Microelectronics, 245-248, 2007
Design Space exploration of FPGA-based accelerators with multi-level parallelism
G Zhong, A Prakash, S Wang, Y Liang, T Mitra, S Niar
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
HOG feature extractor hardware accelerator for real-time pedestrian detection
M Hemmati, M Biglari-Abhari, S Berber, S Niar
2014 17th Euromicro Conference on Digital System Design, 543-550, 2014
Pets: Power and energy estimation tool at system-level
SK Rethinagiri, O Palomar, O Unsal, A Cristal, R Ben-Atitallah, S Niar
Fifteenth International Symposium on Quality Electronic Design, 535-542, 2014
Multilevel MPSoC simulation using an MDE approach
RB Atitallah, E Piel, S Niar, P Marquet, JL Dekeyser
2007 IEEE International SOC Conference, 197-200, 2007
Adaptive video-based algorithm for accident detection on highways
B Maaloul, A Taleb-Ahmed, S Niar, N Harb, C Valderrama
2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES …, 2017
Hybrid system level power consumption estimation for fpga-based mpsoc
SK Rethinagiri, RB Atitallah, S Niar, E Senn, JL Dekeyser
2011 IEEE 29th International Conference on Computer Design (ICCD), 239-246, 2011
An MPSoC architecture for the multiple target tracking application in driver assistant system
J Khan, S Niar, A Menhaj, Y Elhillali, JL Dekeyser
2008 International Conference on Application-Specific Systems, Architectures …, 2008
Performance evaluation and design tradeoffs of on-chip interconnect architectures
M Bakhouya, S Suboh, J Gaber, T El-Ghazawi, S Niar
Simulation Modelling Practice and Theory 19 (6), 1496-1505, 2011
A Reliability Study on CNNs for Critical Embedded Systems
M Neggaz, P Ribalta, I Alouani, S Niar
The 36th IEEE International Conference on Computer Design ICCD, 2018
An efficient power estimation methodology for complex risc processor-based platforms
SK Rethinagiri, R Ben Atitallah, JL Dekeyser, E Senn, S Niar
Proceedings of the great lakes symposium on VLSI, 239-244, 2012
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