| QCAPro-an error-power estimation tool for QCA circuit design S Srivastava, A Asthana, S Bhanja, S Sarkar 2011 IEEE international symposium of circuits and systems (ISCAS), 2377-2380, 2011 | 324 | 2011 |
| Estimation of upper bound of power dissipation in QCA circuits S Srivastava, S Sarkar, S Bhanja IEEE transactions on nanotechnology 8 (1), 116-127, 2008 | 214 | 2008 |
| MRAM PUF: A novel geometry based magnetic PUF with integrated CMOS J Das, K Scott, S Rajaram, D Burgett, S Bhanja IEEE Transactions on Nanotechnology 14 (3), 436-443, 2015 | 100 | 2015 |
| Probabilistic error modeling for nano-domain logic circuits T Rejimon, K Lingasubramanian, S Bhanja IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (1), 55-65, 2008 | 95 | 2008 |
| Scalable probabilistic computing models using Bayesian networks T Rejimon, S Bhanja 48th Midwest Symposium on Circuits and Systems, 2005., 712-715, 2005 | 77 | 2005 |
| Field-coupled nanocomputing NG Anderson, S Bhanja Springer Berlin Heidelberg, 2014 | 75 | 2014 |
| QCA circuits for robust coplanar crossing S Bhanja, M Ottavi, F Lombardi, S Pontarelli Journal of Electronic Testing 23, 193-210, 2007 | 75 | 2007 |
| Switching activity estimation of VLSI circuits using Bayesian networks S Bhanja, N Ranganathan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (4), 558-567, 2003 | 74 | 2003 |
| Non-Boolean computing with nanomagnets for computer vision applications S Bhanja, DK Karunaratne, R Panchumarthy, S Rajaram, S Sarkar Nature nanotechnology 11 (2), 177-183, 2016 | 70 | 2016 |
| Probabilistic modeling of QCA circuits using Bayesian networks S Bhanja, S Sarkar IEEE Transactions on Nanotechnology 5 (6), 657-670, 2006 | 64 | 2006 |
| Hierarchical probabilistic macromodeling for QCA circuits S Srivastava, S Bhanja IEEE Transactions on Computers 56 (2), 174-190, 2007 | 60 | 2007 |
| Low power magnetic quantum cellular automata realization using magnetic multi-layer structures J Das, SM Alam, S Bhanja IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (3 …, 2011 | 57 | 2011 |
| Magnetic cellular automata coplanar cross wire systems JF Pulecio, S Bhanja Journal of applied physics 107 (3), 2010 | 51 | 2010 |
| Ultra-low power hybrid CMOS-magnetic logic architecture J Das, SM Alam, S Bhanja IEEE Transactions on Circuits and Systems I: Regular Papers 59 (9), 2008-2016, 2012 | 49 | 2012 |
| An accurate probabilistic model for error detection T Rejimon, S Bhanja 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 44 | 2005 |
| Novel designs for thermally robust coplanar crossing in QCA S Bhanja, M Ottavi, F Lombardi, S Pontarelli Proceedings of the Design Automation & Test in Europe Conference 1, 6 pp., 2006 | 40 | 2006 |
| Dependency preserving probabilistic modeling of switching activity using Bayesian networks S Bhanja, N Ranganathan Proceedings of the 38th annual Design Automation Conference, 209-214, 2001 | 39 | 2001 |
| Survey of emerging technology based physical unclonable funtions IA Bautista Adames, J Das, S Bhanja Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 317-322, 2016 | 36 | 2016 |
| Magnetic cellular automata wire architectures JF Pulecio, PK Pendru, A Kumari, S Bhanja IEEE transactions on nanotechnology 10 (6), 1243-1248, 2011 | 33 | 2011 |
| Probabilistic error model for unreliable nano-logic gates T Rejimon, S Bhanja 2006 Sixth IEEE Conference on Nanotechnology 1, 47-50, 2006 | 29 | 2006 |
Sudeep SarkarDistinguished University Professor, Computer Science and Engineering, University of South FloridaПотвърден имейл адрес: usf.edu
