chenming hu
chenming hu
Потвърден имейл адрес: eecs.berkeley.edu - Начална страница
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
D Hisamoto, WC Lee, J Kedzierski, H Takeuchi, K Asano, C Kuo, ...
IEEE transactions on electron devices 47 (12), 2320-2325, 2000
Hot-electron-induced MOSFET degradation-model, monitor, and improvement
C Hu, SC Tam, FC Hsu, PK Ko, TY Chan, KW Terrill
IEEE Journal of Solid-State Circuits 20 (1), 295-305, 1985
MoS2 transistors with 1-nanometer gate lengths
SB Desai, SR Madhvapathy, AB Sachid, JP Llinas, Q Wang, GH Ahn, ...
Science 354 (6308), 99-102, 2016
A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors
KK Hung, PK Ko, C Hu, YC Cheng
IEEE Transactions on Electron Devices 37 (3), 654-665, 1990
Modern semiconductor devices for integrated circuits
C Hu
Prentice Hall 2, 9-24, 2010
Sub 50-nm finfet: Pmos
X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ...
International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999
FinFET scaling to 10 nm gate length
B Yu, L Chang, S Ahmed, H Wang, S Bell, CY Yang, C Tabery, C Ho, ...
Digest. International Electron Devices Meeting,, 251-254, 2002
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
Y Cao, T Sato, M Orshansky, D Sylvester, C Hu
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No …, 2000
Hole injection SiO/sub 2/breakdown model for very low voltage lifetime extrapolation
KF Schuegraf, C Hu
IEEE transactions on electron devices 41 (5), 761-767, 1994
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
C Hu, TJ King, V Subramanian, L Chang, X Huang, YK Choi, ...
US Patent 6,413,802, 2002
Electrical breakdown in thin gate and tunneling oxides
IC Chen, SE Holland, C Hu
IEEE journal of Solid-state Circuits 20 (1), 333-342, 1985
MOSFET modeling & BSIM3 user’s guide
Y Cheng, C Hu
Springer Science & Business Media, 1999
MOS capacitance measurements for high-leakage thin dielectrics
KJ Yang, C Hu
IEEE Transactions on Electron Devices 46 (7), 1500-1501, 1999
Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI
F Assaderaghi, D Sinitsky, SA Parke, J Bokor, PK Ko, C Hu
IEEE Transactions on Electron Devices 44 (3), 414-422, 1997
Sub-50 nm P-channel FinFET
X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ...
IEEE Transactions on Electron Devices 48 (5), 880-886, 2001
Lucky-electron model of channel hot-electron injection in MOSFET's
S Tam, PK Ko, C Hu
IEEE transactions on electron devices 31 (9), 1116-1125, 1984
Enhanced ferroelectricity in ultrathin films grown directly on silicon
SS Cheema, D Kwon, N Shanker, R Dos Reis, SL Hsu, J Xiao, H Zhang, ...
Nature 580 (7804), 478-482, 2020
Threshold voltage model for deep-submicrometer MOSFETs
ZH Liu, C Hu, JH Huang, TY Chan, MC Jeng, PK Ko, YC Cheng
IEEE Transactions on electron devices 40 (1), 86-95, 1993
Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology
YC Yeo, TJ King, C Hu
Journal of applied physics 92 (12), 7266-7271, 2002
Immersion fluid for immersion lithography, and method of performing immersion lithography
YC Yeo, BJ Lin, C Hu
US Patent 7,700,267, 2010
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