| New algorithms for the rectilinear Steiner tree problem JM Ho, G Vijayan, CK Wong IEEE transactions on computer-aided design of integrated circuits and …, 1990 | 206 | 1990 |
| Optimal node ranking of trees AV Iyer, HD Ratliff, G Vijayan Information Processing Letters 28 (5), 225-229, 1988 | 134 | 1988 |
| On an edge ranking problem of trees and graphs AV Iyer, HD Ratliff, G Vijayan Discrete Applied Mathematics 30 (1), 43-52, 1991 | 111 | 1991 |
| Layer assignment for multichip modules JM Ho, M Sarrafzadeh, G Vijayan, CK Wong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990 | 92 | 1990 |
| Library-less synthesis for static CMOS combinational logic circuits Gavrilov, Glebov, Pullela, Dharchoudhury, Panda, Vijayan, Blaauw 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 71 | 1997 |
| Rectilinear graphs and their embeddings G Vijayan, A Wigderson SIAM Journal on Computing 14 (2), 355-372, 1985 | 66 | 1985 |
| ALI: A procedural language to describe VLSI layouts RJ Lipton, SC North, J Valdes, G Vijayan, R Sedgewick 19th Design Automation Conference, 467-474, 1982 | 54 | 1982 |
| A new approach to the rectilinear Steiner tree problem J Ho, G Vijayan, CK Wong Proceedings of the 26th ACM/IEEE Design Automation Conference, 161-166, 1989 | 50 | 1989 |
| A new method for floor planning using topological constraint reduction G Vijayan, RS Tsay IEEE transactions on computer-aided design of integrated circuits and …, 1991 | 45 | 1991 |
| A neighborhood improvement algorithm for rectilinear Steiner trees N Hasan, G Vijayan, CK Wong IEEE International Symposium on Circuits and Systems, 2869-2872, 1990 | 43 | 1990 |
| Parallel assembly of modular products-an analysis AV LYER Technical Report PDRC, Technical Report, 1988 | 43 | 1988 |
| Worst case analysis of a graph coloring algorithm JP Spinrad, G Vijayan Discrete Applied Mathematics 12 (1), 89-92, 1985 | 27 | 1985 |
| VLSI layout as programming RJ Lipton, J Valdes, G Vijayan, SC North, R Sedgewick ACM Transactions on Programming Languages and Systems (TOPLAS) 5 (3), 405-421, 1983 | 27 | 1983 |
| Optimized test application timing for AC test VS Iyengar, G Vijayan IEEE transactions on computer-aided design of integrated circuits and …, 1992 | 26 | 1992 |
| Fast/sub 14/Technology: design technology for the automation of multi-gigahertz digital logic S Horne, D Glowka, S McMahon, P Nixon, M Seningen, G Vijayan 2004 International Conference on Integrated Circuit Design and Technology …, 2004 | 25 | 2004 |
| Geometry of planar graphs with angles V Vijayan Proceedings of the second annual symposium on Computational geometry, 116-124, 1986 | 24 | 1986 |
| Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree JM Ho, G Vijayan, CK Wong 1989 IEEE International Conference on Computer-Aided Design, 6, 7, 8, 9-6, 7 …, 1989 | 22 | 1989 |
| Partitioning logic on graph structures to minimize routing cost G Vijayan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990 | 21 | 1990 |
| Generalization of min-cut partitioning to tree structures and its applications G Vijayan IEEE Transactions on Computers 40 (03), 307-314, 1991 | 19 | 1991 |
| Min-cost partitioning on a tree structure and applications G Vijayan Proceedings of the 26th ACM/IEEE Design Automation Conference, 771-774, 1989 | 19 | 1989 |
