Chadwin D. Young
Chadwin D. Young
Потвърден имейл адрес: utdallas.edu - Начална страница
Large ferroelectric polarization of TiN/Hf0. 5Zr0. 5O2/TiN capacitors due to stress-induced crystallization at low thermal budget
SJ Kim, D Narayan, JG Lee, J Mohan, JS Lee, J Lee, HS Kim, YC Byun, ...
Applied Physics Letters 111 (24), 2017
Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning
PD Kirsch, P Sivasubramani, J Huang, CD Young, MA Quevedo-Lopez, ...
Applied Physics Letters 92 (9), 2008
The effect of interfacial layer properties on the performance of Hf-based gate stack devices
G Bersuker, CS Park, J Barnett, PS Lysaght, PD Kirsch, CD Young, ...
Journal of Applied Physics 100 (9), 2006
Mechanism of Electron Trapping and Characteristics of Traps in Gate Stacks
G Bersuker, JH Sim, CS Park, CD Young, SV Nadkarni, R Choi, BH Lee
IEEE Transactions on Device and Materials Reliability 7 (1), 138-145, 2007
Effect of film thickness on the ferroelectric and dielectric properties of low-temperature (400° C) Hf0. 5Zr0. 5O2 films
SJ Kim, J Mohan, J Lee, JS Lee, AT Lucero, CD Young, L Colombo, ...
Applied Physics Letters 112 (17), 2018
High-k gate stacks for planar, scaled CMOS integrated circuits
HR Huff, A Hou, C Lim, Y Kim, J Barnett, G Bersuker, GA Brown, ...
Microelectronic Engineering 69 (2-4), 152-167, 2003
Conventional n-channel MOSFET devices using single layer HfO/sub 2/and ZrO/sub 2/as high-k gate dielectrics with polysilicon gate electrode
Y Kim, G Gebara, M Freiler, J Barnett, D Riley, J Chen, K Torres, JE Lim, ...
International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001
Interfacial layer-induced mobility degradation in high-k transistors
G Bersuker, J Barnett, N Moumen, B Foran, CD Young, P Lysaght, ...
Japanese journal of applied physics 43 (11S), 7899, 2004
Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric
G Bersuker, D Heh, C Young, H Park, P Khanal, L Larcher, A Padovani, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Dipole Moment Model Explaining nFET Vt Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics
P Sivasubramani, TS Boscke, J Huang, CD Young, PD Kirsch, ...
2007 IEEE Symposium on VLSI Technology, 68-69, 2007
Electron trap generation in high-/spl kappa/gate stacks by constant voltage stress
CD Young, D Heh, SV Nadkarni, R Choi, JJ Peterson, J Barnett, BH Lee, ...
IEEE Transactions on Device and Materials Reliability 6 (2), 123-131, 2006
Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)
BH Lee, CD Young, R Choi, JH Sim, G Bersuker, CY Kang, R Harris, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance–voltage analysis
P Zhao, A Khosravi, A Azcatl, P Bolshakov, G Mirabelli, E Caruso, ...
2D Materials 5 (3), 031002, 2018
Effect of pre-existing defects on reliability assessment of high
G Bersuker, JH Sim, CD Young, R Choi, PM Zeitzoff, GA Brown
Microelectron. Reliabil 44 (5), 1509-1512, 2004
Bias dependence of total ionizing dose effects in SiGe-MOS FinFETs
GX Duan, CX Zhang, EX Zhang, J Hachtel, DM Fleetwood, RD Schrimpf, ...
IEEE Transactions on Nuclear Science 61 (6), 2834-2838, 2014
Spatial distributions of trapping centers in HfO2∕ SiO2 gate stacks
D Heh, CD Young, GA Brown, PY Hung, A Diebold, G Bersuker, EM Vogel, ...
Applied physics letters 88 (15), 2006
Pulsed Methodology and Its Application to Electron-Trapping Characterization and Defect Density Profiling
CD Young, Y Zhao, D Heh, R Choi, BH Lee, G Bersuker
IEEE Transactions on electron devices 56 (6), 1322-1329, 2009
Effects of ALD HfO2 thickness on charge trapping and mobility
JH Sim, SC Song, PD Kirsch, CD Young, R Choi, DL Kwong, BH Lee, ...
Microelectronic Engineering 80, 218-221, 2005
Experimental Evidence of the Fast and Slow Charge Trapping/Detrapping Processes in High- k Dielectrics Subjected to PBTI Stress
D Heh, CD Young, G Bersuker
IEEE electron device letters 29 (2), 180-182, 2008
Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer
P Bolshakov, P Zhao, A Azcatl, PK Hurley, RM Wallace, CD Young
Applied Physics Letters 111 (3), 2017
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Статии 1–20