| Representative critical reliability paths for low-cost and accurate on-chip aging evaluation S Wang, J Chen, M Tehranipoor IEEE/ACM Intl. Conf. Computer-Aided Design (ICCAD), 2012 | 65 | 2012 |
| Efficient Selection and Analysis of Critical-Reliability Paths and Gates J Chen, S Wang, M Tehranipoor GLSVLSI Proceedings of the great lakes symposium on VLSI, pp. 45-50, 2012 | 40 | 2012 |
| Design of reliable SoCs with BIST hardware and machine learning M Sadi, GK Contreras, J Chen, LR Winemberg, M Tehranipoor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (11 …, 2017 | 18 | 2017 |
| Critical Paths Selection and Test Cost Reduction Considering Process Variations J Chen, M Tehranipoor IEEE Asian Test Symposium (ATS), 2013 | 16 | 2013 |
| Critical-reliability path identification and delay analysis J Chen, S Wang, M Tehranipoor ACM Journal on Emerging Technologies in Computing Systems (JETC) 10 (2), 1-21, 2014 | 15 | 2014 |
| A Framework for Fast and Accurate Critical-Reliability Paths Identification J Chen, S Wang, N Bidokhti, M Tehranipoor North Atlantic Test Workshop, 2011 | 12 | 2011 |
| BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning M Sadi, G Contreras, D Tran, J Chen, LR Winemberg, M Tehranipoor 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 9 | 2016 |
| A Novel Flow for Reducing Clock Skew Considering NBTI Effect and Process Variations J Chen, M Tehranipoor The International Symposium on Quality Electronic Design (ISQED), 2013 | 9 | 2013 |
| Information theoretic modeling and analysis for global interconnects with process variations SZ Denic, B Vasic, CD Charalambous, J Chen, JM Wang IEEE transactions on very large scale integration (VLSI) systems 19 (3), 397-410, 2009 | 5 | 2009 |
| The Study of Parameters of BP Network for Pattern Recognition J Chen, F Fu, Y Wang | 5* | 2006 |
| Life After Failure N Bidokhti, M Tehranipoor, J Chen, J Lee Reliability and Maintainability Symposium (RAMS), 2014 | 4 | 2014 |
| A Novel Integrated Reliability Test System for BEOL TDDB Study J Chen, P Song, TM Shaw, F Stellari, L Gignac, C Breslin, D Pfeiffer, ... Proc. of International Symposium for Test and Failure Analysis (ISTFA), 2012 | 3 | 2012 |
| FPGA Realization of the Decimation Filter in Software Radio Y Liu, L Jin, J Chen | 3* | 2006 |
| Identification of Testable Representative Paths for Low-Cost Verification of Circuit Performance During Manufacturing Tests and in the Field J Chen, L Winemberg, M Tehranipoor IEEE VLSI Test Symposium (VTS) 2014, 2014 | 2 | 2014 |
| Power supply noise sensor J Chen, DT Tran, AM Jarrar, JA Corso, LR Winemberg, B Rajasekaran US Patent 10,084,437, 2018 | 1 | 2018 |
| Integrated time dependent dielectric breakdown reliability testing J Chen, D Pfeiffer, TM Shaw, P Song, F Stellari US Patent 9,874,601, 2018 | 1 | 2018 |
| Integrated time dependent dielectric breakdown reliability testing J Chen, D Pfeiffer, TM Shaw, P Song, F Stellari US Patent 9,448,277, 2016 | 1 | 2016 |
| The DSP Implementation of Signal Synchronization on the Petrolic Numerically Controlled Log S Yonghui, F Fenglin, C Jian, C Jifeng | 1* | 2006 |
| Integrated time dependent dielectric breakdown reliability testing J Chen, D Pfeiffer, TM Shaw, P Song, F Stellari US Patent 9,939,486, 2018 | | 2018 |
| Critical-Path Selection and Silicon Data Analysis Q Shi, J Chen, M Tehranipoor SRC TECHCON, 2013 | | 2013 |
Mark M. TehranipoorIntel Charles E. Young Endowed Chair Professor, ECE, University of FloridaVerified email at ufl.edu
