Следене
Nozomu Togawa
Nozomu Togawa
Потвърден имейл адрес: waseda.jp
Заглавие
Позовавания
Позовавания
Година
Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier
K Hasegawa, M Yanagisawa, N Togawa
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
1272017
A score-based classification method for identifying hardware-trojans at gate-level netlists
M Oya, Y Shi, M Yanagisawa, N Togawa
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 465-470, 2015
1142015
Hardware Trojans classification for gate-level netlists based on machine learning
K Hasegawa, M Oya, M Yanagisawa, N Togawa
2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016
1132016
Scan-based attack against elliptic curve cryptosystems
R Nara, N Togawa, M Yanagisawa, T Ohtsuki
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 407-412, 2010
942010
Hardware Trojans classification for gate-level netlists using multi-layer neural networks
K Hasegawa, M Yanagisawa, N Togawa
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System …, 2017
882017
Scan-based side-channel attack against RSA cryptosystems using scan signatures
R Nara, K Satoh, M Yanagisawa, T Ohtsuki, N Togawa
IEICE transactions on fundamentals of electronics, communications and …, 2010
872010
A scan-based attack based on discriminators for AES cryptosystems
R Nara, N Togawa, M Yanagisawa, T Ohtsuki
IEICE transactions on fundamentals of electronics, communications and …, 2009
572009
Dynamically changeable secure scan architecture against scan-based side channel attack
Y Atobe, Y Shi, M Yanagisawa, N Togawa
2012 International SoC Design Conference (ISOCC), 155-158, 2012
522012
Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm
K Shimizu, T Ishikawa, N Togawa, T Ikenaga, S Goto
2005 International Conference on Computer Design, 503-510, 2005
492005
Exact and fast l1 cache simulation for embedded systems
N Tojo, N Togawa, M Yanagisawa, T Ohtsuki
2009 Asia and South Pacific Design Automation Conference, 817-822, 2009
422009
A hardware-Trojan classification method using machine learning at gate-level netlists based on Trojan features
K Hasegawa, M Yanagisawa, N Togawa
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2017
372017
Maple: a simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays
N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 1994
371994
Designing hardware trojans and their detection based on a SVM-based approach
T Inoue, K Hasegawa, M Yanagisawa, N Togawa
2017 IEEE 12th international conference on ASIC (ASICON), 811-814, 2017
352017
Scan-based attack against DES cryptosystems using scan signatures
H Kodera, M Yanagisawa, N Togawa
2012 IEEE Asia Pacific Conference on Circuits and Systems, 599-602, 2012
342012
Secure scan design with dynamically configurable connection
Y Atobe, Y Shi, M Yanagisawa, N Togawa
2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing …, 2013
302013
Robust secure scan design against scan-based differential cryptanalysis
Y Shi, N Togawa, M Yanagisawa, T Ohtsuki
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (1), 176-181, 2011
302011
Hardware trojan detection utilizing machine learning approaches
K Hasegawa, Y Shi, N Togawa
2018 17th IEEE International Conference On Trust, Security And Privacy In …, 2018
242018
An Ising model mapping to solve rectangle packing problem
K Terada, D Oku, S Kanamaru, S Tanaka, M Hayashi, M Yamaoka, ...
2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2018
242018
A hardware/software cosynthesis system for digital signal processor cores
N Togawa, M Yanagisawa, T Ohtsuki
IEICE transactions on fundamentals of electronics, communications and …, 1999
241999
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs
N Togawa, M Yanagisawa, T Ohtsuki
IEEE transactions on computer-aided design of integrated circuits and …, 1998
231998
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Статии 1–20